HW: Design a washing machine controller.
The circuit has:
• Three external inputs:
1. START
2. FULL
3. EMPTY
(These signals are 1 for at most a single clock cycle)
• Four outputs:
1. TURN
2. HOT (hot mater)
3. COLD (cold water)
4. DRAIN
• Down counter: which is clocked by a separate clock pulse each minute. The counter has a single output ZERO which is 1 whenever the counter contains value zero and is 0 otherwise. Moreover, the
counter has three inputs:
1. RESET: synchronous reset.
2. LOAD: synchronous load
3. DEC:
The counter synchronously decrements once each minute for DEC = 1, but can be loaded or synchronously reset.
• Panel dial: which indicates how many minutes the wash cycle is to last.
The controller begins when it receives the STRT signal and goes through four distinct cycles:
1. WASH: Assume that the circuit is in its power up state IDLE. If START is 1 for a clock cycle, HOT become 1 and remains 1 until FULL = 1, filling the washer with hot water. Next, using
LOAD, the down counter is loaded with a value from the panel dial. DEC and TURN then become 1 and the washer washes its contents. When ZERO becomes 1, the wash is complete, and TURN and
DEC become 0.
2. SPIN: Next, DRAIN becomes 1, draining the wash water. When EMPTY becomes 1, the down counter is loaded with 7. DEC and TURN then become 1 and the remaining wash water is wrung
from the contents. When ZERO becomes 1, DRAIN, DEC, and TURN return to 0.
3. RINSE: Next, COLD becomes 1 and remains 1 until FULL = 1, filling the washer with cold rinse water. Next, using LOAD, the down counter is loaded with value 10. DEC and TURN then become
1 and the washer rinses its contents. When ZERO becomes 1, the rinse is complete, and TURN and DEC become 0.
4. SPIN: Next, DRAIN becomes 1, draining the rinse water. When EMPTY becomes 1, the down counter is loaded with 8. DEC and TURN then become 1 and the remaining rinse water is wrung from
the contents. When ZERO becomes 1, DRAIN, DEC, and TURN return to 0 and the circuit returns to state IDLE.
.
(a) Find the ASM chart for this controller.
(b) Write the VHDL implementation for this ASM chart.
